| Pad | Module Pin | GPIO / Alt Names | Dir | Analog / RTC | Common Peripherals | Internal Pulls | Strap | Status | Notes |
|---|---|---|---|---|---|---|---|---|---|
| 1 | GND |
— | — | — | — | — | — | Power/NC | Ground |
| 2 | 3V3 |
— | — | — | — | — | — | Power/NC | Power supply 3.3 V |
| 3 | EN |
EN | Input | — | Chip enable | Internal pull-up | No | Power/NC | Active‑high enable. Keep high for normal operation. |
| 4 | SENSOR_VP |
GPIO36 / ADC1_CH0 / RTC_GPIO0 | Input only | ADC1_CH0, RTC | — | No internal PU/PD | No | Input‑only | Good for analog input; not output capable. |
| 5 | SENSOR_VN |
GPIO39 / ADC1_CH3 / RTC_GPIO3 | Input only | ADC1_CH3, RTC | — | No internal PU/PD | No | Input‑only | Good for analog input; not output capable. |
| 6 | IO34 |
GPIO34 / ADC1_CH6 / RTC_GPIO4 | Input only | ADC1_CH6, RTC | — | No internal PU/PD | No | Input‑only | Input only; no PU/PD. |
| 7 | IO35 |
GPIO35 / ADC1_CH7 / RTC_GPIO5 | Input only | ADC1_CH7, RTC | — | No internal PU/PD | No | Input‑only | Input only; no PU/PD. |
| 8 | IO32 |
GPIO32 / ADC1_CH4 / TOUCH9 / RTC_GPIO9 | I/O | ADC1_CH4, Touch9, RTC | XTAL_32K_P | PU/PD via GPIO matrix | No | Available | Also 32.768 kHz crystal input. |
| 9 | IO33 |
GPIO33 / ADC1_CH5 / TOUCH8 / RTC_GPIO8 | I/O | ADC1_CH5, Touch8, RTC | XTAL_32K_N | PU/PD via GPIO matrix | No | Available | Also 32.768 kHz crystal output. |
| 10 | IO25 |
GPIO25 / DAC1 / ADC2_CH8 / RTC_GPIO6 | I/O | DAC1, ADC2_CH8, RTC | EMAC_RXD0 | PU/PD via GPIO matrix | No | Available | ADC2 shared with Wi‑Fi; avoid analog during Wi‑Fi. |
| 11 | IO26 |
GPIO26 / DAC2 / ADC2_CH9 / RTC_GPIO7 | I/O | DAC2, ADC2_CH9, RTC | EMAC_RXD1 | PU/PD via GPIO matrix | No | Available | ADC2 shared with Wi‑Fi. |
| 12 | IO27 |
GPIO27 / ADC2_CH7 / TOUCH7 / RTC_GPIO17 | I/O | ADC2_CH7, Touch7, RTC | EMAC_RX_DV | PU/PD via GPIO matrix | No | Available | ADC2 shared with Wi‑Fi. |
| 13 | IO14 |
GPIO14 / ADC2_CH6 / TOUCH6 / MTMS | I/O | ADC2_CH6, Touch6 | HSPI CLK, SD_CLK, EMAC_TXD2 | PU/PD via GPIO matrix | No | Available | JTAG MTMS by default; free after boot. |
| 14 | IO12 |
GPIO12 / ADC2_CH5 / TOUCH5 / MTDI | I/O | ADC2_CH5, Touch5 | HSPIQ, SD_DATA2 | Internally pulled (strap) | Yes (VDD_SDIO voltage) | Strapping Available | Strapping; default pull‑down on chip; WROVER forces 1.8 V SDIO. Avoid driving at boot. |
| 15 | GND |
— | — | — | — | — | — | Power/NC | Ground |
| 16 | IO13 |
GPIO13 / ADC2_CH4 / TOUCH4 / MTCK | I/O | ADC2_CH4, Touch4 | HSPID, SD_DATA3 | PU/PD via GPIO matrix | No | Available | JTAG MTCK at boot; free after boot. |
| 17 | SHD/SD2* |
GPIO9 / HS1_DATA2 | I/O | — | Connected to SPI flash/PSRAM | — | No | Flash/PSRAM | Used internally by flash/PSRAM; do not use. |
| 18 | SWP/SD3* |
GPIO10 / HS1_DATA3 | I/O | — | Connected to SPI flash/PSRAM | — | No | Flash/PSRAM | Used internally by flash/PSRAM; do not use. |
| 19 | SCS/CMD* |
GPIO11 / HS1_CMD | I/O | — | Connected to SPI flash/PSRAM | — | No | Flash/PSRAM | Used internally by flash/PSRAM; do not use. |
| 20 | SCK/CLK* |
GPIO6 / HS1_CLK | I/O | — | Connected to SPI flash/PSRAM | — | No | Flash/PSRAM | Used internally by flash/PSRAM; do not use. |
| 21 | SDO/SD0* |
GPIO7 / HS1_DATA0 | I/O | — | Connected to SPI flash/PSRAM | — | No | Flash/PSRAM | Used internally by flash/PSRAM; do not use. |
| 22 | SDI/SD1* |
GPIO8 / HS1_DATA1 | I/O | — | Connected to SPI flash/PSRAM | — | No | Flash/PSRAM | Used internally by flash/PSRAM; do not use. |
| 23 | IO15 |
GPIO15 / MTDO | I/O | — | HSPI CS0, U0TXD log control | Internally pulled‑up (strap) | Yes (Log/SDIO timing) | Strapping Available | Strapping; avoid conflicting levels during boot. |
| 24 | IO2 |
GPIO2 | I/O | — | HSPI/SDIO data | Internally pulled‑down (strap) | Yes (boot mode) | Strapping Available | Must be left floating/high for normal SPI boot. |
| 25 | IO0 |
GPIO0 | I/O | — | Boot mode select | Internally pulled‑up (strap) | Yes (boot mode) | Strapping Available | Low at reset → download boot; high → normal boot. |
| 26 | IO4 |
GPIO4 / TOUCH0 | I/O | Touch0 | HS2_DATA2, EMAC_TX_ER | PU/PD via GPIO matrix | — | Available | Usable general‑purpose pin. |
| 27 | NC |
— | — | — | — | — | — | Power/NC | No connect |
| 28 | NC |
— | — | — | — | — | — | Power/NC | No connect |
| 29 | IO5 |
GPIO5 | I/O | — | VSPI CS0, EMAC_RX_CLK | Internally pulled‑up (strap) | Yes (SDIO timing) | Strapping Available | Strapping; don’t pull low unintentionally at boot. |
| 30 | IO18 |
GPIO18 | I/O | — | VSPI CLK | PU/PD via GPIO matrix | No | Available | General‑purpose high‑speed capable. |
| 31 | IO19 |
GPIO19 | I/O | — | VSPI MISO/U0CTS | PU/PD via GPIO matrix | No | Available | General‑purpose pin. |
| 32 | NC |
— | — | — | — | — | — | Power/NC | No connect |
| 33 | IO21 |
GPIO21 | I/O | — | I2C SDA (typical), EMAC_TX_EN | PU/PD via GPIO matrix | No | Available | Good for I²C SDA. |
| 34 | RXD0 |
GPIO3 / U0RXD | I/O | — | UART0 RX (console) | PU/PD via GPIO matrix | No | Available | Used for serial console; free after boot if no logs. |
| 35 | TXD0 |
GPIO1 / U0TXD | I/O | — | UART0 TX (console) | PU/PD via GPIO matrix | No | Available | Boot logs default here; can be repurposed. |
| 36 | IO22 |
GPIO22 | I/O | — | I2C SCL (typical), U0RTS | PU/PD via GPIO matrix | No | Available | Good for I²C SCL. |
| 37 | IO23 |
GPIO23 | I/O | — | VSPI MOSI, HS1_STROBE | PU/PD via GPIO matrix | No | Available | General‑purpose high‑speed capable. |
| 38 | GND |
— | — | — | — | — | — | Power/NC | Ground |
| — | 3V3 | — | — | — | — | — | — | Power/NC | 3.3 V supply |
| — | GND | — | — | — | — | — | — | Power/NC | Ground |
| — | EN | EN (CHIP_EN) | Input | — | Chip enable | Internal pull‑up | No | Power/NC | Active‑high; keep high for normal operation. |
| 36 | GPIO36 | GPIO36 / ADC1_CH0 / RTC_GPIO0 | Input only | ADC1_CH0, RTC | — | No internal PU/PD | No | Input‑only Available | Preferred for ADC1. Cannot drive output. |
| 39 | GPIO39 | GPIO39 / ADC1_CH3 / RTC_GPIO3 | Input only | ADC1_CH3, RTC | — | No internal PU/PD | No | Input‑only Available | Preferred for ADC1. Cannot drive output. |
| 34 | GPIO34 | GPIO34 / ADC1_CH6 / RTC_GPIO4 | Input only | ADC1_CH6, RTC | — | No internal PU/PD | No | Input‑only Available | Preferred for ADC1. Cannot drive output. |
| 35 | GPIO35 | GPIO35 / ADC1_CH7 / RTC_GPIO5 | Input only | ADC1_CH7, RTC | — | No internal PU/PD | No | Input‑only Available | Preferred for ADC1. Cannot drive output. |
| 32 | GPIO32 | GPIO32 / ADC1_CH4 / RTC_GPIO9 | I/O | ADC1_CH4, RTC | — | PU/PD via GPIO matrix | No | Available | Preferred for ADC1. |
| 33 | GPIO33 | GPIO33 / ADC1_CH5 / RTC_GPIO8 | I/O | ADC1_CH5, RTC | — | PU/PD via GPIO matrix | No | Available | Preferred for ADC1. |
| 25 | GPIO25 | GPIO25 | I/O | DAC1, ADC2_CH8 | — | PU/PD via GPIO matrix | No | Available | ADC2 shared with Wi‑Fi; avoid analog during Wi‑Fi. |
| 26 | GPIO26 | GPIO26 | I/O | DAC2, ADC2_CH9 | — | PU/PD via GPIO matrix | No | Available | ADC2 shared with Wi‑Fi. |
| 27 | GPIO27 | GPIO27 | I/O | ADC2_CH7, TOUCH7, RTC | — | PU/PD via GPIO matrix | No | Available | ADC2 shared with Wi‑Fi. |
| 12 | GPIO12 / MTDI | GPIO12 / ADC2_CH5 / TOUCH5 / MTDI | I/O | ADC2_CH5, Touch5 | HSPIQ/SD_DATA2 | Internally pulled (strap) | Yes | Strapping Available | Strap: VDD_SDIO voltage; keep benign at boot. |
| 13 | GPIO13 / MTCK | GPIO13 / ADC2_CH4 / TOUCH4 / MTCK | I/O | ADC2_CH4, Touch4 | HSPID/SD_DATA3 | PU/PD via GPIO matrix | No | Available | JTAG MTCK default; free after boot. |
| 14 | GPIO14 / MTMS | GPIO14 / ADC2_CH6 / TOUCH6 / MTMS | I/O | ADC2_CH6, Touch6 | HSPI CLK/SD_CLK | PU/PD via GPIO matrix | No | Available | JTAG MTMS default; free after boot. |
| 15 | GPIO15 / MTDO | GPIO15 / MTDO | I/O | — | HSPI CS0, U0TXD log ctrl | Internally pulled‑up (strap) | Yes | Strapping Available | Strap; avoid conflicting levels at boot. |
| 0 | GPIO0 | GPIO0 | I/O | ADC2_CH1 | Boot mode select | Internally pulled‑up (strap) | Yes | Strapping Available | Low at reset → download boot; high → normal. |
| 2 | GPIO2 | GPIO2 | I/O | ADC2_CH2, TOUCH2 | HSPI/SDIO data | Internally pulled‑down (strap) | Yes | Strapping Available | Keep high/floating for normal SPI boot. |
| 4 | GPIO4 | GPIO4 / TOUCH0 | I/O | TOUCH0, ADC2_CH0 | HS2_DATA2, EMAC_TX_ER | PU/PD via GPIO matrix | Yes | Strapping Available | Often used as strap in chip docs; keep benign at boot. |
| 5 | GPIO5 | GPIO5 | I/O | — | VSPI CS0, EMAC_RX_CLK | Internally pulled‑up (strap) | Yes | Strapping Available | Strap; avoid pulling low at boot. |
| 16 | GPIO16 | GPIO16 | I/O | — | UART2 RX/TX (usable), GP CLK | PU/PD via GPIO matrix | No | Available | General‑purpose; often used for UART. |
| 17 | GPIO17 | GPIO17 | I/O | — | UART2 RX/TX (usable), GP CLK | PU/PD via GPIO matrix | No | Available | General‑purpose; often used for UART. |
| 18 | GPIO18 | GPIO18 | I/O | — | VSPI CLK | PU/PD via GPIO matrix | No | Available | High‑speed capable. |
| 19 | GPIO19 | GPIO19 | I/O | — | VSPI MISO / U0CTS | PU/PD via GPIO matrix | No | Available | General‑purpose. |
| 21 | GPIO21 | GPIO21 | I/O | — | I2C SDA (typical) | PU/PD via GPIO matrix | No | Available | Good for I²C SDA. |
| 22 | GPIO22 | GPIO22 | I/O | — | I2C SCL (typical) | PU/PD via GPIO matrix | No | Available | Good for I²C SCL. |
| 23 | GPIO23 | GPIO23 | I/O | — | VSPI MOSI | PU/PD via GPIO matrix | No | Available | High‑speed capable. |
| 1 | GPIO1 / U0TXD | GPIO1 / U0TXD | I/O | — | UART0 TX (console) | PU/PD via GPIO matrix | No | Available | Boot logs by default; can repurpose. |
| 3 | GPIO3 / U0RXD | GPIO3 / U0RXD | I/O | — | UART0 RX (console) | PU/PD via GPIO matrix | No | Available | Used for console; free after boot if unused. |
| 6 | GPIO6 | GPIO6 | I/O | — | SPI Flash CLK (default) | — | No | Flash/PSRAM | Usable only if not connected to external flash (rare). |
| 7 | GPIO7 | GPIO7 | I/O | — | SPI Flash SD0 (default) | — | No | Flash/PSRAM | Usable only if not connected to external flash (rare). |
| 8 | GPIO8 | GPIO8 | I/O | — | SPI Flash SD1 (default) | — | No | Flash/PSRAM | Usable only if not connected to external flash (rare). |
| 9 | GPIO9 | GPIO9 | I/O | — | SPI Flash SD2 (default) | — | No | Flash/PSRAM | Usable only if not connected to external flash (rare). |
| 10 | GPIO10 | GPIO10 | I/O | — | SPI Flash SD3 (default) | — | No | Flash/PSRAM | Usable only if not connected to external flash (rare). |
| 11 | GPIO11 | GPIO11 | I/O | — | SPI Flash CMD (default) | — | No | Flash/PSRAM | Usable only if not connected to external flash (rare). |
Device selector: “ESP32‑WROVER (module)” shows only pins actually broken out on the WROVER module; “Generic ESP32 (chip)” shows the full ESP32 GPIO map, including pins typically wired to external flash (GPIO6–GPIO11).
Notes & Caveats
Sources (see official documentation):